The present invention is related to a structure and a manufacturing method of a capacitor, and especially to a structure and a manufacturing method of a capacitor applied to the dynamic random access memory (DRAM).
It is well known that the capacity of a capacitor is related to the quality of dynamic random access memory (DRAM). Therefore, many methods have been developed for increasing the capacity of a capacitor.
First of all, please refer to FIGS. 1(a) and (b) showing a conventional method for manufacturing a capacitor. This method is described in detail as follows.
Shown in FIG. 1(a) includes the steps of (1) forming an interlayer dielectric (ILD) 11 over a silicon substrate 10 by chemical vapor deposition (CVD) or lower pressure chemical vapor deposition (LPCVD), (2) defining a contact window by photolithography and partially removing the ILD 11 to form the contact window 12, (3) forming a doped polysilicon layer 13 with a thickness of 1000 xc3x85 over the ILD 11 and in the contact window 12 by LPCVD, and (4) forming a rugged polysilicon layer 14 with a thickness of 850 xc3x85 over the doped polysilicon layer 13 to increase the surface area of the capacitor.
In FIG. 1(b), the steps include: (1) defining the capacitor region by photolithography and partially etching the rugged polysilicon layer 14 and the doped polysilicon layer 13 to expose a portion of the ILD 11; (2) forming an oxide-on-nitride-on-oxide (ONO) layer 15 on the rugged polysilicon layer 14 and the ILD 11 and alongside the doped polysilicon layer 13 by LPCVD; and (3) forming another doped polysilicon layer 16 over the ONO layer 15 to construct the conventional capacitor.
Please refer to FIG. 2 showing another conventional method. The detailed steps are illustrated as follows.
In FIG. 2(a), the steps include: (1) forming an interlayer dielectric (ILD) 21 over a silicon substrate 20 by chemical vapor deposition (CVD), (2) forming a silicon nitride 22 on ILD 21, wherein the silicon nitride 22 has a thickness of 100 xc3x85xcx9c300 xc3x85 and serves as an etching stop layer, (3) forming a sacrificial oxide 23 on the silicon nitride 22 by CVD, (4) defining a contact window by photolithography and partially removing the ILD 21, the silicon nitride 22, and the sacrificial oxide 23 to form the contact window 24, and (5) forming a doped polysilicon layer 25 with a thickness of 1000 xc3x85 over the sacrificial oxide 23 and in the contact window 24 by LPCVD.
In FIG. 2(b), the steps include: (1) defining the capacitor region by photolithography and partially etching the doped polysilicon layer 25; (2) etching the sacrificial oxide 23 by using a buffer oxide etchant (B.O.E.) containing hydrofluoric acid (HF) to expose the silicon nitride 22; (3) forming an oxide-on-nitride-on-oxide (ONO) layer 26 on the silicon nitride 22 and a top and sidewalls of the doped polysilicon layer 25 by LPCVD; and (4) forming another doped polysilicon layer 27 on the ONO layer 26 to construct the capacitor.
In addition, there is another method as shown in FIG. 3. This method is described as follows.
In FIG. 3(a), the steps include: (1) forming an interlayer dielectric (ILD) 31 over a silicon substrate 30 by CVD, (2) forming a silicon nitride 32 on ILD 31, wherein the silicon nitride 32 has a thickness of 100 xc3x85xcx9c300 xc3x85 and serves as an etching stop layer, (3) forming a first sacrificial oxide 33 on the silicon nitride 32 by CVD, (4) defining a contact window by photolithography and partially removing the first sacrificial oxide 33, the silicon nitride 32, and the ILD 31 to form the contact window 34, (5) forming a first doped polysilicon layer 35 with a thickness of 1000 xc3x85 over the first sacrificial oxide 33 and in the contact window 34 by LPCVD, and (6) forming a second sacrificial oxide 36 on the first doped polysilicon layer 35 by CVD.
In FIG. 3(b), the steps include: (1) defining the capacitor region by photolithography and partially etching the second sacrificial oxide 36, the first doped polysilicon layer 35, and the first sacrificial oxide 33, wherein the silicon nitride 32 serves as an etching stop layer; (2) forming a second doped polysilicon layer 37 on the top surface of the second sacrificial oxide 36, alongside the second sacrificial oxide 36, the first doped polysilicon layer 35, and the first sacrificial oxide 33, as well as on the silicon nitride 32.
In FIG. 3(c), the second doped polysilicon layer 37 is etched by dry etching (i.e. an anisotropic etching) to expose the top surface of the second sacrificial oxide 36 and a portion of the silicon nitride 32.
In FIG. 3(d), the second sacrificial oxide 36 is completely removed by using a buffer oxide etchant (B.O.E.) containing hydrofluoric acid (HF) to expose the first doped polysilicon layer 35. Thereafter, an oxide-on-nitride-on-oxide (ONO) layer 38 is formed over the portion of the silicon nitride 32, the second doped polysilicon layer 37, and the first doped polysilicon layer 35 by LPCVD. Finally, another doped polysilicon layer 39 is formed on the ONO layer 38 to construct the capacitor.
However, these conventional methods have some defects described as follows:
1. In FIGS. 1(a) and (b), the rugged polysilicon layer in the fixed capacitor region can not effectively increase the surface area of the capacitor. Therefore, the maximum capacity can be only increased up to two times by such a method using the rugged polysilicon layer for increasing the surface area of capacitor. Because the size of the capacitor will be getting smaller in the future, this method may be no longer effective then.
2. In the method of FIGS. 2(a) and (b), the sacrificial oxide is formed and then is etched for increasing the surface area of the capacitor, but the effect is not good enough for the future requirements.
3. In the method as shown in FIGS. 3(a)xcx9c(d), the cylindrical doped polysilicon can increase the surface area of the capacitor which is constructed by a doped polysilicon layer, the ONO layer, and another doped polysilicon layer. Such a structure can increase the total surface area effectively and also provide the solution in the requirements of capacitance below 0.18 um generation of DRAM area. However, it can be seen from FIG. 3(d) that the surface of the capacitor is so irregular that it will seriously influence the subsequent planarization process of the semiconductor.
An object of the present invention is to provide a manufacturing method which can effectively increase the density and intensity of the capacitor applied to the memory unit with high density.
Another object of the present invention is to provide a structure and a manufacturing method for promoting the yield rate of a capacitor.
In the preferred embodiment of the present invention, the method for manufacturing a capacitor, applied to a memory unit including a substrate forming thereon a dielectric layer forming thereon an etching stop layer, includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer over tops and sidewalls of the portion of the first conducting layer and the portion of the sacrificial layer, f) forming an intermediate layer with a rugged structure on said second conducting layer; g) removing said intermediate layer with said rugged structure and partially removing said second conducting layer while retaining a portion of said second conducting layer alongside said portion of said first conducting layer and transferring said rugged structure of said intermediate layer to a rough top surface on said portion of the first conducting layer, thereby exposing said portion of said sacrificial layer; and h) removing said portion of said sacrificial layer to expose said etching stop layer, wherein said portions of said first and second conducting layers with said rough top surface serve as a capacitor plate.
In accordance with one aspect of the present invention, the dielectric layer is formed by a chemical vapor deposition (CVD).
In accordance with another aspect of the present invention, the dielectric layer is a nondoped silicon glass (NSG) layer with a thickness ranging between 1000 xc3x85 and 3000 xc3x85.
In accordance with another aspect of the present invention, the etching stop layer is formed by a chemical vapor deposition. The etching stop layer is a silicon nitride layer with a thickness ranging between 100 xc3x85 and 300 xc3x85.
In accordance with another aspect of the present invention, in the step (a), the sacrificial layer is formed by a chemical vapor deposition. Preferably, the sacrificial layer is a sacrificial oxide with a thickness more than 6000 xc3x85.
In accordance with another aspect of the present invention, in the step (b), the contact window is formed by a photolithographic and etching technique.
In accordance with another aspect of the present invention, in the step (c), the first conducting layer is formed by a chemical vapor deposition. Preferably, the first conducting layer can be a doped polysilicon layer or a doped amorphous silicon layer, and has a thickness ranging between 1000 xc3x85 and 3000 xc3x85.
In accordance with another aspect of the present invention, in the step (d), the first conducting layer and the sacrificial layer are partially removed by a photolithographic and etching technique.
In accordance with another aspect of the present invention, in the step (e), the second conducting layer is formed by a chemical vapor deposition. Preferably, the second conducting layer can be a doped polysilicon layer or a doped amorphous silicon layer, and has a thickness ranging between 1000 xc3x85 and 3000 xc3x85.
In accordance with another aspect of the present invention, in the step (f), the intermediate layer is a rugged polysilicon layer formed by a low pressure chemical vapor deposition (LPCVD) under a temperature ranging between 560xc2x0 C. and 580xc2x0 C. The step (f) further includes a step to perform a treatment of phosphoric acid for enhancing a rough surface of the intermediate layer.
This method further includes a step after the step (f) to execute an ion implantation on the intermediate layer by using one of arsenic (As) and phosphorus (P).
In accordance with another aspect of the present invention, in the step (g), the intermediate layer and the second conducting layer are removed by an anisotropic etching.
In accordance with another aspect of the present invention, in the step (g), the portion of the sacrificial layer is removed by a wet etching using a buffer oxide etchant (B.O.E.) solution containing hydrofluoric acid (HF).
After the step (h), this method further includes the steps of forming an additional dielectric layer over the etching stop layer, the first conducting layer, and the second conducting layer, and forming a third conducting layer over the additional dielectric layer to serve as another capacitor plate.
In accordance with another aspect of the present invention, the additional dielectric layer and the third conducting layer are formed by a low pressure chemical vapor deposition (LPCVD).
In accordance with another aspect of the present invention, the additional dielectric layer is an oxide-on-nitride-on-oxide (ONO) layer with a thickness ranging between 50 xc3x85 and 200 xc3x85.
In accordance with another aspect of the present invention, the third conducting layer is a doped polysilicon layer.
According to the present invention, the capacitor includes a structure formed in the dielectric layer and the etching stop layer and forming a contact window, and a conducting layer filling in the contact window and upwardly extended to form a generally reversed cylindrical structure with a rough top surface, including a horizontal part and a vertical part where the horizontal part has an end thereof extended and the space between the horizontal part and the etching stop layer are adapted to be occupied by a dielectric layer and a conducting layer, to serve as a capacitor plate.
In addition, the capacitor further includes an additional dielectric layer formed over the conducting layer, and an additional conducting layer formed over the additional dielectric layer to serve as another capacitor plate.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which: